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LPC4370 ACDHS speed and DMA
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LPC4370 ACDHS speed
AHB clock BASE_M4_CLK CLK_M4_ADCHS up to 204 MHz. For register interface.
ADCHS clock BASE_ADCHS_CLK CLK_ADCHS up to 80MHz For conversion rate.
How do I set up the BASE_M4_CLK or the AHB clocks for high speed ADC?
How do I verify the BASE_ADCHS_CLK is running (204Mhz ) fast enough for 80Msample?
But in reality, the HSADC clock structure is very simple and can be setup by directly setting the HSADC base clock with this one function:
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, BaseClock_XXXX, true, false);
You can attach the HSADC base clock to any of the following clock inputs:
/**
* @brief CGU clock input list
* These are possible input clocks for the CGU and can come
* from both external (crystal) and internal (PLL) sources. These
* clock inputs can be routed to the base clocks (@ref CHIP_CGU_BASE_CLK_T).
*/
typedef enum CHIP_CGU_CLKIN {
CLKIN_32K, /*!< External 32KHz input */
CLKIN_IRC, /*!< Internal IRC (12MHz) input */
CLKIN_ENET_RX, /*!< External ENET_RX pin input */
CLKIN_ENET_TX, /*!< External ENET_TX pin input */
CLKIN_CLKIN, /*!< External GPCLKIN pin input */
CLKIN_RESERVED1,
CLKIN_CRYSTAL, /*!< External (main) crystal pin input */
CLKIN_USBPLL, /*!< Internal USB PLL input */
CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */
CLKIN_MAINPLL, /*!< Internal Main PLL input */
CLKIN_RESERVED2,
CLKIN_RESERVED3,
CLKIN_IDIVA, /*!< Internal divider A input */
CLKIN_IDIVB, /*!< Internal divider B input */
CLKIN_IDIVC, /*!< Internal divider C input */
CLKIN_IDIVD, /*!< Internal divider D input */
CLKIN_IDIVE, /*!< Internal divider E input */
CLKINPUT_PD /*!< External 32KHz input */
} CHIP_CGU_CLKIN_T;
Connect the 204MHz main PLL to a divider input, set the divider to 3, and use the divider for the HSADC base clock.
Gives 204 / 3 = 68Mhz. Just make sure you aren't using those dividers for anything else!
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, ); /* Setup divider A for main PLL rate divided by 3 */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVA, true, false); /* HSADC base clock = divider A input */
Use the USB PLL rate (typically 480MHz) with a divide by 6 to get 80MHz. (Note different dividers have different maximum divider values)
Chip_USB0_Init(); /* Sets USB PLL to 480Mhz */
Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_USBPLL, ); /* Setup divider D for USB PLL rate divided by 6 */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVD, true, false); /* HSADC base clock = divider D input */
I think you might not be getting 20 MHz you will be getting 2MHz, as the only divider that can be sourced from USB0PLL is Divider A
(Max divider value supported by DIV_A is 4), if you attempt to source others [DIV_B to DIV_D] from USB0PLL it will default to IRC (12MHz).
Hence you will get "IRC CLK"/6 as the output. To get 80 MHz you can try the following
Chip_USB0_Init(); /* Initialize the USB0 PLL to 480 MHz */
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, ); /* Source DIV_A from USB0PLL, and set divider to 2 (Max div value supported is 4) [IN 480 MHz; OUT 240 MHz */
Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, ); /* Source DIV_B from DIV_A, [IN 240 MHz; OUT 80 MHz */
Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVB, true, false); /* Source ADHCS base clock from DIV_B */
Chip_Clock_EnableOpts(CLK_ADCHS, true, true, ); /* Enable the clock */ 480MHZ / 2 / 3 = 80 MHZ
Chip_Clock_GetRate(CLK_ADCHS);
Finally I've got some adequate results. ADCHS clock is 80MHz, but sample rate is only 40Msps, not 80Msps as I expected.
Chip_Clock_EnableOpts(CLK_ADCHS, true, true, ); /* Enable the clock */
Every time I've tried to set SAMPLERATE to values more than 4000000 - UART stopped working.
Is it real to get 80Msps?
The original hsadc.c file used TIMER1 to trigger a software event to trigger to start the ADC.
In my modification I tried to us the TIMMER1 to stop the ADC sampling but it did not work.
I found that there were too many IRQ events (with higher priority than the UART) causing the UART not to get service
and also the descriptor would not update.
I left the code in and set the SAMPLERATE to 100 which cause TIMER1 to file every 10ms.
I used this to toggle GPIO port 3 bit 7 for testing.
1111111111111
