fpga之显示字符串

//必须在有效区域下显示颜色才有颜色

显示字符可以在设定一个有效区域内显示

另加两个wire 求出新的x，y
module vga_fpga(
clk,rst_n,
vga_b,vga_g,vga_r,rom_data,rom_addr,
VGA_HS,VGA_VS,
VGA_BLANK_N,VGA_SYNC_N,VGA_CLK
);
input   clk,rst_n;
output  [4:0]  rom_addr;
output  [127:0]rom_data;
output  [7:0]  vga_b;
output  [7:0]  vga_g;
output  [7:0]  vga_r;
output         VGA_BLANK_N ;
output         VGA_HS;
output         VGA_SYNC_N;
output         VGA_VS;
output         VGA_CLK;
/*********************************/
//扫描x,y;
reg [10:0] count_x;//计数列
reg [10:0] count_y;//计数行
always @(posedge clk or negedge rst_n)
if(!rst_n)
count_x <= 1'd0;
else if(count_x == 11'd1056)
count_x <= 1'd0;
else
count_x <= count_x + 1'b1;
always @(posedge clk or negedge rst_n)
if(!rst_n)
count_y <= 1'd0;
else if(count_y == 11'd625)
count_y <= 1'd0;
else if(count_x == 11'd1056)
count_y <= count_y +1'd1;
else
count_y <= count_y;

/************************************/
//行列同步
assign VGA_VS       = (count_y <= 11'd3) ? 1'b0 : 1'b1;
assign VGA_HS       = (count_x <= 11'd80)? 1'b0 : 1'b1;
assign VGA_SYNC_N   = (count_y <= 11'd3) ? 1'b0 : 1'b1;
assign VGA_BLANK_N  = (count_x <= 11'd80)? 1'b0 : 1'b1;
/**************************************/
//是否行列有效
reg isready;
always @(posedge clk or negedge rst_n)
if(!rst_n)
isready <= 1'b0;
else if((count_x > 11'd240 && count_x < 11'd1040)&&(count_y > 11'd24 && count_y < 11'd624))
isready <= 1'b1;
else
isready <= 1'b0;
/************************************/
//x,y坐标
wire [10:0]loca_x;
wire [10:0]loca_y;
assign loca_x = isready ? count_x-11'd240 : 11'd0;
assign loca_y = isready ? count_y-11'd24  : 11'd0;
/*****************************************/
//显示 从第一百行 第一百列开始
//在小矩形框内显示
reg isvalid;
always @(posedge clk or negedge rst_n)
if(!rst_n)
isvalid <= 1'b0;
else if((loca_x > 7'd99 && loca_x < 8'd228)&&(loca_y > 7'd99 && loca_y < 8'd132))
isvalid <= 1'b1;
else isvalid <= 1'b0;
wire [7:0] valid_x;
wire [7:0] valid_y;
assign valid_x = isvalid ? loca_x - 8'd100 :1'd0;
assign valid_y = isvalid ? loca_y - 8'd100 :1'd0;
/*****************************************/
reg [5:0] l;//行
always @(posedge clk or negedge rst_n)
if(!rst_n)
l <= 1'd0;
else if(isready && (valid_y < 7'd32))
l <= valid_y;
// else
// l <= 1'd0;
reg [7:0] h;
always @(posedge clk or negedge rst_n)
if(!rst_n)
h <= 1'd0;
else if(isready && (valid_x < 8'd128))
h <= valid_x;
//else
// h <= 1'd0;
//显示颜色
reg [23:0] vga_s;
always @(posedge clk or negedge rst_n)
if(!rst_n)
vga_s <= 24'd0;
else if( rom_data[7'd127 - h] && isvalid)
vga_s <= 24'hfffafa;  //baise
else if(!rom_data[7'd127 - h] && isvalid)
vga_s <= 24'h008b00;  //绿
else
vga_s <= 24'hffec8b;//huang

/**********************************************/

vga_rom (
.address (rom_addr ),
.clock ( clk ),
.q ( rom_data )
);

assign  rom_addr     = l;
assign  VGA_CLK  = clk;
assign  vga_b        = isready ?  vga_s[7:0]  :8'd0;
assign  vga_g        = isready ?  vga_s[15:8] :8'd0;
assign  vga_r        = isready ?  vga_s[23:16]:8'd0;
endmodule