verilog 仿真时读取txt文件

reg [:]data;
initial begin
# clk =;
forever # clk = ~clk;
end
initial begin
# rst=;
# rst=;
end
reg [:]data_sin[:]; ////改动点数据矩阵长度设置
integer i;
initial
begin
i=;
begin
$readmemb("D:/Chapter_8/E8_1_QAMModem/QAM.txt",data_sin,,); ///改动点数据矩阵长度 注意是“/” 而不是“\”
end
forever
begin
@(posedge clk)
begin
i <= i+;
din <= data_sin[i];
end
end
end
endmodule

fid = fopen('data.txt','w');
for oo=1:1:i
if mod(oo,10) == 0
fprintf(fid,'%f,%f,\n',sI1(oo),sQ1(oo));
else
fprintf(fid,'%f,%f,',sI1(oo),sQ1(oo));
end
end
fclose(fid);

integer file_out;
initial
begin
file_out = $fopen("mI.txt");
if (!file_out) begin
$finish;
end
end wire signed [:] dout_s = fifo_fft_data[:];always @ (posedge clk)
begin
if(fifo_fft_valid)
$fdisplay(file_out, "%d", dout_s);
endinteger file_out_Q;
initial
begin
file_out_Q = $fopen("mQ.txt");
if (!file_out_Q) begin
$finish;
end
end wire signed [:] dout_s_Q = fifo_fft_data[:];always @ (posedge clk)
begin
if(fifo_fft_valid)
$fdisplay(file_out_Q, "%d", dout_s_Q);
end

对应以上文件的matlab 读取数据：

%读取FPGA仿真出的数据
clc;
clear;close all;fid=fopen('mI.txt','r');
[di,N]=fscanf(fid,'%lg',inf);
fclose(fid);
fid=fopen('mQ.txt','r');
[dq,N]=fscanf(fid,'%lg',inf);
fclose(fid);
exp1=di+dq*1i;
% exp2 = exp1(25000:30000);
% exp2 = exp1(1024:8192);
exp2 = exp1;
plot(di);
figure;
plot(dq);
figure;
plot(20*log10(abs(fft((exp2).* window(@gausswin,length(exp2),4)))));