自定义AXI总线形式SPI接口IP核，点亮OLED

`timescale 1ns / 1ps module spi_4wire#(parameter DIV_CYC = )
(
//本地接口
input clk,//100MHZ
input rst_n,
input [-:] com,//1发送控制信息，2发送数据 其他无效
input [-:] din,
output busy,
//芯片侧接口
output reg sclk = ,
output reg sdin = ,
output reg cs = 'b1,
output reg dc = //1是数据，0是控制命令
);
//**************************参数定义********************************************
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=; bit_depth>; clogb2=clogb2+)
bit_depth = bit_depth >> ;
end
endfunction localparam DIV_CNT_W = clogb2(DIV_CYC-),
BIT_CNT_W = clogb2(-); localparam IDLE = ,
SEND = ,
DONE = ; //************************变量定义****************************************
reg [ (DIV_CNT_W-):] div_cnt = ;
wire add_div_cnt ;
wire end_div_cnt ;
reg [ (BIT_CNT_W-):] bit_cnt = ;
wire add_bit_cnt ;
wire end_bit_cnt ;
reg [-:] state_c = IDLE,state_n = IDLE;
wire idle2send,send2done,done2idle;
reg [+-:] data_tmp = ;
wire din_vld;
wire start_send;
reg busy_flag = ;
//************************逻辑****************************************
//sclk时钟分频 T:10ns --> 200ns 20倍
//分频计数器
always @(posedge clk or negedge rst_n) begin
if (rst_n==) begin
div_cnt <= ;
end
else if(add_div_cnt) begin
if(end_div_cnt)
div_cnt <= ;
else
div_cnt <= div_cnt+ ;
end
end
assign add_div_cnt = ();
assign end_div_cnt = add_div_cnt && div_cnt == (DIV_CYC)- ; //比特计数器
always @(posedge clk or negedge rst_n) begin
if (rst_n==) begin
bit_cnt <= ;
end
else if(add_bit_cnt) begin
if(end_bit_cnt)
bit_cnt <= ;
else
bit_cnt <= bit_cnt+ ;
end
end
assign add_bit_cnt = (state_c == SEND && end_div_cnt);
assign end_bit_cnt = add_bit_cnt && bit_cnt == ()- ; //控制状态机
always @(posedge clk or negedge rst_n) begin
if (rst_n==) begin
state_c <= IDLE ;
end
else begin
state_c <= state_n;
end
end always @(*) begin
case(state_c)
IDLE :begin
if(idle2send )
state_n = SEND ;
else
state_n = state_c ;
end
SEND :begin
if(send2done )
state_n = DONE ;
else
state_n = state_c ;
end
DONE :begin
if(done2idle )
state_n = IDLE ;
else
state_n = state_c ;
end
default : state_n = IDLE ;
endcase
end assign idle2send = state_c==IDLE && (end_div_cnt && data_tmp[- -:] != );
assign send2done = state_c==SEND && (end_bit_cnt);
assign done2idle = state_c==DONE && (end_div_cnt); //输入命令/数据寄存
always @(posedge clk or negedge rst_n)begin
if(rst_n=='b0)begin
data_tmp <= ;
end
else if(din_vld)begin
data_tmp <= {com,din};
end
else if(done2idle)begin
data_tmp <= ;
end
end assign din_vld = busy_flag == 'b0 && com != 2'd0; //SPI输出信号
always @(posedge clk or negedge rst_n)begin
if(rst_n=='b0)begin
sdin <= ;
end
else if(add_bit_cnt)begin
sdin <= data_tmp[--bit_cnt];
end
end always @(posedge clk or negedge rst_n)begin
if(rst_n=='b0)begin
cs <= 'b1;
end
else if(start_send)begin
cs <= ;
end
else if(done2idle)begin
cs <= 'b1;
end
end assign start_send = add_bit_cnt && bit_cnt == ; always @(posedge clk or negedge rst_n)begin
if(rst_n=='b0)begin
dc <= 'b0;
end
else if(start_send)begin
case(data_tmp[:])//1发送控制信息，2发送数据 其他无效
'd1:dc <= 1'b0;//1是数据，0是控制命令
'd2:dc <= 1'b1;
default:dc <= 'b0;
endcase
end
else if(done2idle)begin
dc <= ;
end
end //SCLK
always @(posedge clk or negedge rst_n)begin
if(rst_n=='b0)begin
sclk <= ;
end
else if(add_div_cnt && div_cnt == DIV_CYC/-)begin
sclk <= 'b1;
end
else if(end_div_cnt)begin
sclk <= ;
end
end //本地侧输出
always@(posedge clk or negedge rst_n)begin
if(rst_n == )begin
busy_flag <= ;
end
else if(din_vld)begin
busy_flag <= 'b1;
end
else if(done2idle)begin
busy_flag <= ;
end
end assign busy = busy_flag | din_vld; endmodule

`timescale ns / ps module spi_4wire_w_v1_0 #
(
// Users to add parameters here // User parameters ends
// Do not modify the parameters beyond this line // Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = ,
parameter integer C_S00_AXI_ADDR_WIDTH =
)
(
// Users to add ports here
//SPI signals
output sclk,
output sdin,
output cs,
output dc,
// User ports ends
// Do not modify the ports beyond this line // Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH- : ] s00_axi_awaddr,
input wire [ : ] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH- : ] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/)- : ] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [ : ] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH- : ] s00_axi_araddr,
input wire [ : ] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH- : ] s00_axi_rdata,
output wire [ : ] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
); reg rst_n = 'b1;
wire [-:] din;
wire [-:] com;
wire busy;
wire [-:] data;
wire data_vld; // Instantiation of Axi Bus Interface S00_AXI
spi_4wire_w_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) spi_4wire_w_v1_0_S00_AXI_inst (
.local_dout(data),
.local_dout_vld(data_vld),
.local_busy(busy), .S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
); // Add user logic here
spi_4wire#(.DIV_CYC())
uut
(
.clk (s00_axi_aclk) ,//100MHZ
.rst_n (rst_n) ,
.com (com) ,//1发送控制信息，2发送数据 其他无效
.din (din) ,
.busy (busy) ,//rdy .sclk (sclk) ,
.sdin (sdin) ,
.cs (cs) ,
.dc (dc) //1是数据，0是控制命令
); always@(posedge s00_axi_aclk)begin
rst_n <= s00_axi_aresetn;
end assign com = data_vld ? data[:] : 'd0;
assign din = data_vld ? data[-:] : 'd0;
// User logic ends endmodule

`timescale ns / ps module spi_4wire_w_v1_0_S00_AXI #
(
// Users to add parameters here // User parameters ends
// Do not modify the parameters beyond this line // Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = ,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH =
)
(
// Users to add ports here
output [C_S_AXI_DATA_WIDTH-:] local_dout,
output reg local_dout_vld = ,
input local_busy,
// User ports ends
// Do not modify the ports beyond this line // Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH- : ] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [ : ] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH- : ] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/)- : ] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [ : ] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH- : ] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [ : ] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH- : ] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [ : ] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
); // AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH- : ] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [ : ] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH- : ] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH- : ] axi_rdata;
reg [ : ] axi_rresp;
reg axi_rvalid; // Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/) + ;
localparam integer OPT_MEM_ADDR_BITS = ;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-:] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-:] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-:] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-:] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-:] reg_data_out;
integer byte_index; // I/O Connections assignments assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid; assign local_dout = slv_reg0; always@(posedge S_AXI_ACLK)begin
if( S_AXI_ARESETN == 'b0)
local_dout_vld <= ;
else
local_dout_vld <= slv_reg_wren;
end // Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low. always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
axi_awready <= 'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && ~local_busy)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 'b1;
end
else
begin
axi_awready <= 'b0;
end
end
end // Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid. always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
axi_awaddr <= ;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && ~local_busy)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end // Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low. always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
axi_wready <= 'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && ~local_busy)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 'b1;
end
else
begin
axi_wready <= 'b0;
end
end
end // Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
slv_reg0 <= ;
slv_reg1 <= ;
slv_reg2 <= ;
slv_reg3 <= ;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
'h0:
for ( byte_index = ; byte_index <= (C_S_AXI_DATA_WIDTH/)-; byte_index = byte_index+ )
if ( S_AXI_WSTRB[byte_index] == ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*) +: ] <= S_AXI_WDATA[(byte_index*) +: ];
end
'h1:
for ( byte_index = ; byte_index <= (C_S_AXI_DATA_WIDTH/)-; byte_index = byte_index+ )
if ( S_AXI_WSTRB[byte_index] == ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*) +: ] <= S_AXI_WDATA[(byte_index*) +: ];
end
'h2:
for ( byte_index = ; byte_index <= (C_S_AXI_DATA_WIDTH/)-; byte_index = byte_index+ )
if ( S_AXI_WSTRB[byte_index] == ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*) +: ] <= S_AXI_WDATA[(byte_index*) +: ];
end
'h3:
for ( byte_index = ; byte_index <= (C_S_AXI_DATA_WIDTH/)-; byte_index = byte_index+ )
if ( S_AXI_WSTRB[byte_index] == ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*) +: ] <= S_AXI_WDATA[(byte_index*) +: ];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end // Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction. always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
axi_bvalid <= ;
axi_bresp <= 'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 'b1;
axi_bresp <= 'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 'b0;
end
end
end
end // Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion. always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
axi_arready <= 'b0;
axi_araddr <= 'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 'b0;
end
end
end // Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
axi_rvalid <= ;
axi_rresp <= ;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 'b1;
axi_rresp <= 'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 'b0;
end
end
end // Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
'h0 : reg_data_out <= slv_reg0;
'h1 : reg_data_out <= slv_reg1;
'h2 : reg_data_out <= slv_reg2;
'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= ;
endcase
end // Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 'b0 )
begin
axi_rdata <= ;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end // Add user logic here // User logic ends endmodule

`timescale 1ns / 1ps module axi_spi_tb( ); parameter CYC = ,
RST_TIM = ; reg s00_axi_aclk;
reg s00_axi_aresetn;
reg [-:] s00_axi_awaddr;
wire [-:] s00_axi_awprot;
reg s00_axi_awvalid;
wire s00_axi_awready;
reg [-:] s00_axi_wdata;
reg [-:] s00_axi_wstrb;
reg s00_axi_wvalid;
wire s00_axi_wready;
wire [-:] s00_axi_bresp;
wire s00_axi_bvalid;
wire s00_axi_bready;
reg [-:] s00_axi_araddr;
wire [-:] s00_axi_arprot;
reg s00_axi_arvalid;
wire s00_axi_arready;
wire [-:] s00_axi_rdata;
wire [-:] s00_axi_rresp;
wire s00_axi_rvalid;
wire s00_axi_rready; spi_4wire_w_v1_0 #
( .C_S00_AXI_DATA_WIDTH(),
.C_S00_AXI_ADDR_WIDTH()
)
uut
(
// Users to add ports here
//SPI signals
. sclk (sclk) ,
. sdin (sdin) ,
. cs (cs) ,
. dc (dc) , . s00_axi_aclk (s00_axi_aclk) ,
. s00_axi_aresetn (s00_axi_aresetn) ,
. s00_axi_awaddr (s00_axi_awaddr) ,
. s00_axi_awprot (s00_axi_awprot) ,
. s00_axi_awvalid (s00_axi_awvalid) ,
. s00_axi_awready (s00_axi_awready) ,
. s00_axi_wdata (s00_axi_wdata) ,
. s00_axi_wstrb (s00_axi_wstrb) ,
. s00_axi_wvalid (s00_axi_wvalid) ,
. s00_axi_wready (s00_axi_wready) ,
. s00_axi_bresp (s00_axi_bresp) ,
. s00_axi_bvalid (s00_axi_bvalid) ,
. s00_axi_bready (s00_axi_bready) ,
. s00_axi_araddr (s00_axi_araddr) ,
. s00_axi_arprot (s00_axi_arprot) ,
. s00_axi_arvalid (s00_axi_arvalid) ,
. s00_axi_arready (s00_axi_arready) ,
. s00_axi_rdata (s00_axi_rdata) ,
. s00_axi_rresp (s00_axi_rresp) ,
. s00_axi_rvalid (s00_axi_rvalid) ,
. s00_axi_rready (s00_axi_rready)
); initial begin
s00_axi_aclk = ;
forever #(CYC/2.0) s00_axi_aclk = ~s00_axi_aclk;
end initial begin
s00_axi_aresetn = ;
#;
s00_axi_aresetn = ;
#(RST_TIM*CYC);
s00_axi_aresetn = ;
end assign s00_axi_awprot = 'd0;
assign s00_axi_bready = 'b1;
assign s00_axi_arprot = 'd0;
assign s00_axi_rready = 'b1; initial begin
#;
s00_axi_awaddr = ;
s00_axi_awvalid = ;
s00_axi_wdata = ;
s00_axi_wstrb = ;
s00_axi_wvalid = ;
s00_axi_araddr = ;
s00_axi_arvalid = ;
#(RST_TIM*CYC);
#(CYC*);
s00_axi_awaddr = ;
s00_axi_awvalid = 'b1;
s00_axi_wdata = 'h02_4a;
s00_axi_wstrb = 'b1111;
s00_axi_wvalid = 'b1;
s00_axi_araddr = ;
s00_axi_arvalid = ;
#5_000;
$stop;
end endmodule